1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a structure of a semiconductor device. More specifically, the present invention relates to a method of forming a passivation film of a semiconductor device and a structure of a passivation film of a semiconductor device in which the leakage current between a select source line and a common source line can be reduced significantly.
2. Discussion of Related Art
Generally, a semiconductor memory device is classified into volatile memory devices in which stored information is lost as the supply of power is stopped, and non-volatile memory devices in which information continues kept even when the supply of power is stopped. The non-volatile memory devices include an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory and the like.
The flash memory devices are classified into a NOR type and a NAND type depending upon the configuration of a cell. A cell array region of the NAND type flash memory is composed of a number of strings. One string is connected to 16 or 32 cells. Each string includes a string select transistor, a plurality of cell transistors and a ground select transistor, all of which are serially connected. A drain region of the string select transistor is connected to a bit line and a source region of the ground select transistor is connected to a common source line.
In this NAND type flash memory device, a high density plasma (hereinafter, referred to as ‘HDP’) film is used as a passivation film. The HDP film is formed by a chemical vapor deposition (CVD) method so that between-metal-wires is insulated. However, when the HDP film is deposited by the CVD method, a plasma charge infiltrates into the semiconductor device through the metal wires. This causes the leakage current between the select source line and the common source line to occur over a reference value (for example, 5×10−12A). As between-the select source line and the common source line is isolated by an insulating film, it is required that the leakage current of over a given reference value be not generated. Practically, the leakage current of over a given reference value is not generated in a wafer on which up to a metal wire process is performed. After the HDP film formation process is performed, however, a large amount of the leakage current is generated.